This disclosure generally relates to electronic circuits. The throughput and bandwidth demands on a memory system can vary rapidly in response to the use of different applications. To reduce power consumption, it is desirable to operate a memory interface at the lowest clock frequency possible while delivering adequate performance.
Some memory system designs change the clock frequency of the memory interface based on the changing throughput and bandwidth demands on the memory system. However, these designs suffer from a performance hit because of the long latency required to change the memory interface's clock frequency.